//test_bench
//2015-11-8 14:34:11
//by fengshaui

//sys frequency is 25Mhz   so the cycle is 40ns  

`timescale  1ns/1ns


module uart_baud_generate_tb;

reg         sys_clk_i_tb;
reg         rst_n_baud_tb;
wire        baud_clk_o_tb;

initial begin
    sys_clk_i_tb = 1'b0;
    rst_n_baud_tb = 1'b0;
    
    #100
    rst_n_baud_tb = 1'b1;
    
end 

always #20 sys_clk_i_tb = ~sys_clk_i_tb;


uart_baud_generate uart_baud_generate_inst(
    .sys_clk_i  (sys_clk_i_tb),
    .rst_n_baud (rst_n_baud_tb),
    .baud_clk_o (baud_clk_o_tb)      
);
    
    
endmodule
